Plated wire memory



y P969v woo F. CHOW 3,456,246

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United States Patent 3,456,246 PLATED WIRE MEMORY Woo F. Chow, Horsham, Pa., assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Sept. 28, 1965, Ser. No. 490,926 Int. Cl. Gllb 5/12 US. Cl. 340-174 4 Claims ABSTRACT OF THE DISCLOSURE The present device provides two magnetizable information positions on a plated wire memory for storing one bit of information and in addition thereto provides two magnetizable reference positions for each plated wire as well as two magnetiza-ble flag positions for each plated wire. Each of the magnetizable positions on a plated wire has a drive strap disposed thereacross. When the memory, composed of the plated wires, is interrogated, one drive strap associated with one of the information bit positions and one drive strap associated with one of the reference positions are interrogated as a pair while the remaining two drive straps are interrogated as a pair so that if there is a mismatch there are four voltages added together indicating a mismatch and if there is a match there are no voltages appearing at the output.

This invention relates to a thin-film plated wire memory and more particularly to a content addressable memory. It is especially useful in a content addressable memory which employs a current steering technique.

In the fabrication of one embodiment of a content addressable memory, hereinafter referred to singularly as a CAM, it is the practice to provide two memory locations for storing one bit of information by two magnetic vectors and a third memory location for storing a reference bit. This arrangement has one drive strap for each of the information positions and one drive strap for the reference bit. The system then operates to interrogate the memory by rotating the vector of the reference position and one of the two vectors of the two positions assigned to the information bit. If the interrogating information and the stored information are the same, the one information vector, which is rotated, is arranged to lie in the opposite direction from the reference vector and hence the induced voltages from the rotated vectors will cancel each other. On the other hand, if the interrogating information is different from the stored information, the system is arranged to have the one information vector which is rotated lie in the same direction as the reference vector and hence the induced voltages will be additive. In addition, such a system may have one or more temporary storage positions which can be considered as temporary registers or the flag memory positions for each CAM word. If a match situation has been effected the magnetic vectors of the fiag position will be disposed in one position and if there is a mismatch the magnetic vectors of the flag position will be disposed in another position.

In such a system the best available read-out voltage or the internally generated voltage due to a change of magnetic fiux (which occurs during a mismatch) is only twice the voltage which would be induced by rotating a single memory position vector, since only two induced voltages are added together. The availability of this internally generated voltage which is twice a single induced voltage does not provide the optimum signal to noise ratio, especially if the interrogation signals and the reference signal are not perfectly timed. If the interrogation signal and the reference signal are applied at different times, which may include a simple overlap of time, the induced voltages 3,456,246 Patented July 15, 1969 ice therefrom are not fully cancelled. The uncancelled signals are transmitted along the sense line as noise and the noise level may approach the level of a mismatch signal (two additive voltages). In addition, in a content addressable memory which employs a current steering technique, the available internal generated voltage which is twice a single induced voltage does not provide as large a current steering power as is desirable to steer the flag bit or other data bit according to the system operation of a CAM.'With the additional possibilities of the imperfect timing of the interrogation signals, the available steering power will be decreased to less than twice a single induced power.

The present invention provides an arrangement for increasing the number of additive voltages to four instead of two, when there is a mismatch, and at the same time providing for a cancellation of the signals when there is a match.

Accordingly it is an object of the present invention to provide an improved content addressable memory readout arrangement.

It is another object of the present invention to provide a content addressable memory which has an improved signal to noise ratio.

In accordance with a feature of the present invention there is provided, in addition to the two information straps and the reference signal strap, an additional drive strap. Under this additional drive strap lie the complement vectors of the vectors which lie under the reference strap. Accordingly, both the reference strap and the additional drive strap hereinafter called the reference-complement strap are energized at the same time that both of the information drive straps are energized, so that when there is a mismatch the four voltages which are induced (by the drive signals along two information straps and along the two reference straps) create an improvement of 2 to 1 in voltage over the previous method and an improvement of 4 to 1 in steering power over the previous method.

In accordance with another feature of the present invention the drive strap for flag position is accompanied by a flag-complement drive strap which lies over a group of vectors which represent the complements of the flag vectors. When there is to be a read-out of the flag information both the flag-complement drive strap and the flag drive strap are energized along with the reference and referencecomplement straps to once again give an improvement of 2 to 1 in voltage and an improvement of 4 to 1 in steering power over the previous method.

The above mentioned and other features and objects of the present invention will become apparent by reference to the following description, taken in conjunction with the accompanying drawings in which:

FIGURE 1 is a schematic showing the drive straps including the reference-complement drive strap and the flagcomplement drive strap.

FIGURE 2 is a timing diagram showing the application of the various currents on the drive straps during a search for ONE.

FIGURE 3 is a timing diagram showing the conditions of the currents on the various drive straps during a search for ZERO.

Consider FIGURE 1 which shows a schematic of a plated wire memory arrangement which is fabricated in accordance with the present invention. The write drivers and the sense amplifiers on the right hand side of FIG- URE 1 represent one embodiment as used wtih the con ventional read-write approach. However, if a system employs strictly a current steering technique such write drivers and read amplifiers are not used. In such a technique both ends of the plated wire are grounded and the drive straps are used for the sense means. A write-in is accomplished by using the flag vectors as the drivers.

Such a system is described in my copending application, Ser. No. 466,904. In FIGURE 1, there are depicted three plated wires 11, 13, and 15. Disposed orthogonally to the three plated wires are six drive straps 17 through 22. Drive straps 17 and 18 are labeled D and DC which indicates a data bit drive strap and a data-complement bit drive strap. Although only one data bit is shown in FIG- URE 1, many data bits can be arranged in this manner. The drive straps 19 and 20 are labeled R and RC indieating a reference drive strap and a reference-complement drive strap. The drive straps 21 and 22 are labeled F and FC indicating a flag drive strap and a flag-complement drive strap.

Also indicated in FIGURE 1 are vectors 38 which are indicative of the magnetization vectors which are present at .the. positions as defined by the drive straps and the plated wires. For instance, the memory position 39 defined by the intersection of the drive strap 17 and the plated wire 11 has a magnetization vector oriented vertically up (that is, counter-clockwise as seen from the left end of the wire) while the memory location 40 defined by the drive strap 18 and the plated wire element 11 has a magnetization vector 24 which is oriented vertically down (that is, clockwise seen from the left end of the wire). The combination of the vectors 23 and 24 shall be considered for purposes of discussion as defining a ONE bit of information while the combination of the vectors 25 and 26 will be considered as storing a ZERO.

It will be noted that the vectors which are located in each of the pairs of positions under the reference-complement drive straps are oriented to define ZEROs. Actually the reference vectors are so oriented in order to be complements of a ONE. The foregoing orientation of the reference is so arranged that when the data positions are interrogated for a ONE, the reference positions will induce voltages that oppose the voltages which are induced if a ONE should be present. Hence, there will be no signal generated and therefore a match condition indicated. It should be obvious that the reference magnetic vectors could be oriented in the same manner as vectors 23 and 24 and in that situation the memory would be searched for ZEROs in order to effect a match condition.

The vectors 33 through 38 which are the flag vectors are originally set, in the embodiment shown, to represent a ONE condition although it should be understood that the orientation of the flag vectors is arbitrary, depending upon the orientation of the reference vectors and whether or not the system develops an output signal to signify the presence of a mismatch condition by resetting the flag. Vectors are arranged in the particular fashion shown in FIGURE 1 in order that when the flag condition is interrogated, the system can also use the ref erence vectors as complementary vectors in order to prevent an output signal, if the flag vectors have not been disturbed. At the same time there will be an output signal (having 4 times the power) if the flag vectors have been disturbed.

Assume that a ONE bit of information has been stored in the plated wire memory at locations 39 and 40 as indicated by the vectors 23 and 24. Further, assume that the system is interrogated for a ONE and that the results of the interrogation are to be stored in the flag locations 41 and 42.

Initially the vector 23 is oriented to the position shown by passing a current II from the driver 43 while simultaneously providing current I3 from the write driver 51. The vector 24 is oriented as shown in location 40 by providing I2 from the driver 45 while simultaneously providing the current I4 from the write driver 51. It is the purpose of this system to permit the flag vectors to remain intact if during the interrogation of a data position or a plurality of data positions, the stored information is identical to the interrogation information.

.4 Hence, if We were to interrogate the positions 39 and 40 for a ONE when in fact a ONE was actually stored therein, the flag vectors 33 and 36 should remain unchanged.

Consider in more detail the interrogation of positions 39 and 40 and in conjunction therewith examine FIG- URE 2. In anticipation of an interrogation operation the flag drivers 46 and 47 pass the currents I5 and I6 down the respective F and FC straps. Accordingly, vector 33 is rotated counter-clockwise toward the hard axis of magnetization on the plated wire 11 while the vector 36 is rotated clockwise toward the hard axis of magnetization on plated wire 11. Currents I5 and I6 are shown in FIG- URE 2 as being initially high. At the same time the bit driver 45 and the reference driver 48 respectively generate the currents I2 and 17. The current I2 on the DC strap rotates the vector 24 clockwise towards the hard axis of magnetization while the current I7 on the reference complement drive strap rotates the vector 30 counterclockwise toward the hard axis of magnetization. As can be seen in FIGURE 2 commencing at t1 the drive currents I2 and I7 are permitted to diminish while the currents I1 and I8 are transmitted down the respective drive straps 17 and 19 and hence experience a rise in amplitude. When the currents I1 and 18 are transmitted down their respective drive straps, the vector 23 is rotated counterclockwise toward the hard axis of magnetization while the vector 27 is rotated clockwise toward the hard axis of magnetization. In response to the currents I2 and I7 diminishing, the vector 24 rotates counterclockwise toward the easy axis of magnetization and the vector 30 rotates clockwise toward the easy axis of magnetization. The voltages developed by the rotation of the vectors 23 and 27 are equal and opposite and therefore buck out one an-' other, while the voltages developed by the vectors 24 and 30 are equal and opposite and buck out one another. Hence, there is no net voltage produced by the rotation of the vectors 23, 24, 27 and 30 and therefore there is no steering current transmitted down the line 11 to steer the vectors 33 or 36. It should be noted that when the vector 33 rotates clockwise toward the easy axis of magnetization in response to the current I5 diminishing, it induces a voltage which results in a small current being transmitted along the line 11 but since I5 diminishes after t2, it has no effect. Actually I5 need not be diminished at this time, but could be diminished between 11 and t2. As will be appreciated hereinafter when we discuss a mismatch, the current developed in response to the rotation of vector 33 at t1t2 time is of sufliciently small value that it would not efiect the operation and there would be some saving in time insofar as the repetition rate of interrogation is concerned by allowing the current 15 to diminish at the same time or thereabout that the other four vectors are being rotated.

Continuing with the examination of FIGURE 2 we find that between 12 and t3, I1 and I8 are high and hence the vectors 23 and 27 are rotated toward the hard axis of magnetization. At t3 time the currents I1 and I8 are allowed to diminish thereby allowing the vectors 23 and 27 to swing respectively back to the position shown in FIG- URE 1 while at the same time the currents I2 and 17 are transmitted along their respective drive straps DC and RC. The renewal of the currents I2 and I7 swing the vectors 24 and 30 in opposite directions and hence the net voltage resulting from the rotation of the vectors 23 and 27, as well as the vectors 24 and 30, is again ZEROQAs can be gleaned from FIGURE 2 the cur-rent I6 diminishes after t4 thereby allowing the vector 36 to rotate counterclockwise toward the easy axis of magnetization, but the voltage induced by the rotation of the vector 36 in no way disturbs the magnetized areas on the remainder of the line 11.

Consider now FIGURE 3 which shows the timing of the currents for interrogating for a ZERO. Let us accept for the moment that if a ZERO were stored in the position which is being interrogated and a ONE orientation was given to the vectors of the reference then in response to an interrogation for ZERO there will be no output. In our consideration of FIGURE 3, let us assume that we are interrogating the positions 39 and 40 wherein a ONE is stored, but we are interrogating for a ZERO. Once again the current is held high to move the vector 33 counterclockwise toward the hard axis of magnetization while the vector 36 is rotated clockwise by the current 16 toward the hard axis of magnetization. Interrogation for the ZERO means that I1 from driver 43 will be transmitted along the line D to rotate the vector 23 counterclockwise while the current I7 will be transmitted along the strap RC to rotate the vector 30 counterclockwise toward the hard axis. If we examine FIGURE 3 we find at 11 time the current I1 and 17 are allowed to diminish thereby allowing the vectors 23 and 30 to rotate.clockwise toward the easy axis of magnetization. If we look at FIGURE 4, which is graphic illustration of the induced voltage assignment, we find that a vector rotation which is clockwise induces a negative voltage. At the same time (i.e., t1 time) as can be seen in FIGURE 3, I2 and I8 are generated to respectively move the vectors 24 and 27 clockwise. Clockwise rotation of vectors 24 and 27 also provides a negative induced voltage as can be seen in FIGURE 4 and hence there are four negative induced voltages on the line 11. The currents of the voltages just described are transmitted along the line 11 to effect the steering of the vector 33. Consider for the moment that the voltage induced by the rotation of the vector 33 is also negative which indicates a voltage that is opposing the movement of the vector, hence the four negative induced voltages as previously described will oppose the movement of the vector, hence the four negative induced voltages as previously described will oppose the movement of the vector 33 and will in fact cause it to rotate into the bottom left-hand quadrant and assume the position of vector 33d depicted inFIGURE 1.

Between time 12 and t3, the current I2 and I8, respectively, hold the vectors 24 and 27 substantially close to the hard axis of magnetization. Commencing at time 13, the currents I2 and I8 are allowed to diminish thereby allowing the vectors 24 and 27 to rotate counterclockwise which, according to the ground rule of FIGURE 4, induce a positive voltage upon line 11. At the same time between times t3 and t4 the currents I1 and I7 are transmitted along their respective drive straps to cause the vectors 23 and 30 to be rotated counterclockwise which as also can be gleaned from FIGURE 4 induce voltages of positive polarity. Hence, there are four positive voltages induced on the line 11 which oppose the movement of the vector 36 and actually cause the vector 36 to be moved into the upper left-hand quadrant and assume the vector position 36a. In effect then the vectors 33 and 36 have been switched indicating that there is a mismatch.

With these vectors 33 and 36 switched, by comparison it can be seen that they now assume the same directions as the vectors 27 and 30. Now if it is decided that the system wants to provide a large output signal upon the interrogation of the flag position, when there has been a mismatch, then the vectors 27 and 33 will first be rotated toward the hard axis and when they are allowed to return, the vectors 30 and 36 will be driven toward the hard axis thus providing four positively induced voltages on the line 11. On the other hand if the system is designed to provide no output from the flag position when there has been a mismatch then the vectors 30 and 33a will be rotated together and allowed to fall together at the same time that the vectors 27 and 36a are rotated.

While I have described above the principles of my invention in connection with specific apparatus, it is to he clearly understood that this description is made only by way of example and not as a limitation of the scope of my invention as set forth in the objects thereof and in the accompanying claims.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A content addressable memory comprising:

(a) a plurality of groups of magnetizable elements for storing information in the form of magnetic vectors wherein said magnetic vectors assume alternatively first and second positions;

(b) at least two of said magnetizable elements being assigned to store one entity of binary information, wherein the induced voltages resulting from disturbing the magnetic states of said magnetic elements would oppose one another;

(c) at least two of said magnetizable elements being assigned to store one entity of reference information, wherein the induced voltages resulting from disturbing the magnetic states of said last mentioned magnetic elements would oppose one another, and wherein one of said magnetizable elements storing reference information and one of said magnetic elements storing binary information form a first pair of magnetizable elements, while the other magnetizable element storing reference information and the other magnetizable element storing binary information form a second pair of magnetizable elements;

(d) drive signal means disposed in close proximity to said magnetizable elements storing said binary information and to said magnetizable elements storing reference information to transmit a signal therealong for the purpose of inducing signals by first disturbing the magnetic states of said first pair of magnetizable elements and secondly disturbing the magnetic states of said second pair of magnetizable elements; and

(e) sensing means coupled to said magnetizable elements to detect whether said binary information is a ONE or a ZERO, in response to said induced signals.

2. A content addressable memory comprising:

(a) a plurality of groups of magnetizable elements for storing information in the form of magnetic vectors wherein said magnetic vectors assume alternatively first and second positions;

(b) at least two of said magnetizable elements being assigned to store one entity of binary information, wherein the induced voltages resulting from disturbing the magnetic states of said magnetic elements would oppose one another;

(c) at least two of said magnetizable elements being assigned to store one entity of reference information, wherein the induced voltages resulting from disturbing the magnetic states of said last mentioned magnetic elements would oppose one another, and wherein one of said magnetic elements storing reference information and one of the magnetic elements storing binary information form a pair of magnetizable elements while the other magnetizable element storing the reference information and the other magnetizable element storing binary information form a second pair of magnetizable elements;

(d) sensing means coupled to said magnetizable elements;

(e) drive signal means disposed in close proximity to said magnetizable elements storing said binary information and to said magnetizable elements storing the reference information to transmit a signal therealong for the purpose of inducing signals in said sensing means by first disturbing said first pair of magnetizable elements and secondly disturbing said second pair of magnetizable elements, whereby said sensing means detects whether or not the induced signals cancel one another.

3. A content addressable memory comprising:

(a) a plurality of groups of magnetizable elements for storing information in the form of magnetic vectors wherein said magnetic vectors assume alternatively first and second positions;

(b) first and second magnetizable elements being assigned to store one entity of binary information, wherein the magnetic vector of said first magnetizable element lies in said first position and wherein the magnetic vector of said second magnetizable element lies in said second position;

(c) third and fourth magnetizable elements being assigned to store one entity of reference information, wherein said third magnetizable element has a magnetic vector which lies in said second position and said fourth magnetizable element as a magnetic vector which lies in said first position;

(d) sensing means coupled to said magnetizable element;

(c) drive signal means disposed in close proximity to said magnetizable elements for storing said binary information and to said magnetizable element storing reference information to transmit a signal therealong for the purpose of inducing a signal in said sensing means by first disturbing said second and fourth magnetizable elements and secondly disturbing said first and third magnetizable elements, whereby said sensing means detects whether said induced signals cancel one another.

4. A content addressable memory comprising:

(a) a plurality of magnetizable elements for storing information in the form of magnetic vectors wherein said magnetic vectors assume alternatively first and second positions;

(b) at least two of said magnetizable elements being assigned to store one entity of binary information, wherein the induced voltages resulting from disturbing the magnetic states of said magnetic elements would oppose one another;

(c) at least two others of said magnetizable elements being assigned to store one entity of reference information, wherein the induced voltages resulting from disturbing the magnetic states of said last mentioned magnetic elements would oppose one another;

(d) at least two of said magnetizable elements being assigned to store one entity of indicator information, wherein the induced voltages resulting from disturbing the magnetic states of said last mentioned magnetic elements would oppose one another, and wherein one of said magnetizable elements storing reference information along with one of said magnetizable elements storing binary information in further conjunction with one of said magnetizable elements storing indicator information are associated together to form one group While the other magnetizable elements storing binary information along with the other magnetizable elements storing reference information in conjunction with the other magnetizable element storing indicator information are associated together to form a second group;

(e) sensing means coupled to said magnetizable elements;

(f) drive signal means disposed in close proximity to said magnetizable element storing said binary information, storing said reference information and storing said indicator information to transmit a signal therealong for the purpose of including signals in said sensing means by disturbing according to said groups of magnetic states of said last mentioned groups of magnetizable elements, whereby said sensing means detects whether said binary information is a ONE or a ZERO in accordance with the resultant information stored by said indicator magnetizable elements.

References Cited UNITED STATES PATENTS 3,311,901 3/1967 Fedde et a1. 340-74 JAMES w. MOFFITI, Primary Examiner 

